An FPGA Based Generic Framework for High Speed Sum of Absolute Difference Implementation

In this paper we present a hardware architecture for the Sum of Absolute Difference (SAD) technique. This paper also gives the design details and the implementation results for an FPGA based core that permits realisation of a high speed matching algorithm for real time image processing applications. The matching criterion chosen is the SAD algorithm The implementation provides the correct position of the target within the frame/image. The ease of implementation lies in the fact that the core is highly parameterized and therefore can cater effectively to the needs of different sizes and resolutions of images and filters. The high speed and the low area of silicon usage make it useful for a number of image processing applications. The paper also gives a review of different hardware architectures.